Low power design for FIR filter

This paper compares three low power schemes for the multi-hierarchy pipeline design of fixed point finite impulse response (FIR) digital filters, and we adopt an optimal CSD encoding method, minimizing the number of adders/subtractions in the design. In addition, a 16-bit, 16 taps low-pass FIR filter is designed to investigate the performance of the three different algorithms. To evaluate the performance of them, the designs are synthesized in SMIC 65nm library. The evaluation shows that the optimal CSD scheme is better than the other two low-power methods at the same throughput.