{"title":"亚微米范围内选择性电镀埋入金线的电化学平面化","authors":"M. Chan, T. Lo","doi":"10.1109/TENCON.1995.496396","DOIUrl":null,"url":null,"abstract":"A planar Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.","PeriodicalId":425138,"journal":{"name":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Electrochemical planarization by selective electroplating for embedded gold wiring in the sub-micron range\",\"authors\":\"M. Chan, T. Lo\",\"doi\":\"10.1109/TENCON.1995.496396\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A planar Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.\",\"PeriodicalId\":425138,\"journal\":{\"name\":\"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings\",\"volume\":\"2002 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENCON.1995.496396\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENCON.1995.496396","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Electrochemical planarization by selective electroplating for embedded gold wiring in the sub-micron range
A planar Au metallization process by electrolytic plating has been developed for metal interconnections in the submicron range. Gold wires with high aspect ratio were fabricated in an embedded structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the gold wires can be selectively formed within the dielectric. This process can provide desired properties of conductor structures for Si LSI applications.