0.4mm3无电池无晶体神经记录SoC实现1.6cm后向散射范围2mm×2mm片上天线

Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao
{"title":"0.4mm3无电池无晶体神经记录SoC实现1.6cm后向散射范围2mm×2mm片上天线","authors":"Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao","doi":"10.1109/vlsitechnologyandcir46769.2022.9830235","DOIUrl":null,"url":null,"abstract":"We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 0.4mm3 Battery-Less Crystal-Less Neural-Recording SoC Achieving 1.6cm Backscattering Range with 2mm×2mm On-Chip Antenna\",\"authors\":\"Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830235\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830235\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830235","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

我们展示了一种全集成的无电池无晶体神经记录SoC,其整体尺寸为0.4mm3。提出了一种基于抖动的三阶互调(IM3)技术,以防止无线电力传输阻塞器(WPT)的后向散射信号,利用2mm×2mm片上天线实现了1.6cm的通信距离。同时,一种二阶互调(IM2)无线锁技术实现了低功耗无晶时钟的产生。在体内测试表明,我们的芯片记录的神经信号与有线测试波形(包括尖峰)相匹配,并且所提出的技术将功耗降低到53.2μW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.4mm3 Battery-Less Crystal-Less Neural-Recording SoC Achieving 1.6cm Backscattering Range with 2mm×2mm On-Chip Antenna
We demonstrate an all-integrated battery-less crystal-less neural-recording SoC featuring an overall size of 0.4mm3. A dither-based 3rd-order intermodulation (IM3) technique is proposed to prevent the backscattering signal from the blocker of wireless power transfer (WPT), achieving a communication range of 1.6cm with a 2mm×2mm on-chip antenna. Meanwhile, a 2nd-order intermodulation (IM2) wireless-lock technique realizes low-power crystal-less clock generation. In-vivo testing shows that the neural signals recorded by our chip matches the wired testing waveforms including spikes, and the proposed techniques reduce the power consumption to 53.2μW.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信