Shruti Konwar, Thockchom Birjit Singha, Soumik Roy, Reginald H. Vanlalchaka
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Adiabatic logic based low power multiplexer and demultiplexer
Minimizing power of digital circuits is always the first priority for VLSI designers. Following this trend, this paper presents a CMOS-based new design approach for a low power adiabatic 8:1 Multiplexer and 1:8 Demultiplexer. Some standard adiabatic logic styles like PFAL, ECRL, 2n2n2p are investigated, which are bettered by the proposed logic. The simulation is carried out in NI-Multisim software at 0.5 μm CMOS technology for frequency range 200MHz - 800MHz.
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