四元数复对数系统

M. Arnold, J. Cowles, Vassilis Paliouras, I. Kouretas
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引用次数: 8

摘要

众所周知的实数到复数算术(两个实数)的推广进一步扩展到更模糊的四元数算术(四个实数),它在信号处理、航空航天、图形学和虚拟现实中都有应用。四元数乘法实现了3D旋转,但代价很高(通常需要16次浮点乘法和12次加法)。本文提出了一种使用对数的四元数表示法来减少乘法开销。真正的对数系统(LNS)允许在嵌入式和基于fpga的系统中快速和廉价的乘法和除法。复杂LNS (CLNS)的最新进展[5]使得快速对数极复数表示变得可以承受。尽管四元数对数函数也定义良好,但简化乘法(与实对数和复对数一样)是没有用的,因为四元数乘法不是交换的,但四元数加法是交换的。为了克服这个问题,我们提出了一种新的四元数复数(QCLNS)表示,使用一对四元数。这种表示法仅使用8个LNS乘法器(即定点加法器)和2个CLNS加法器的理论最小值[11]和[15]来实现四元数乘法。因为CLNS数字比普通的矩形复数表示更紧凑,所以单精度QCLNS比传统的四元数表示少占用10.9%的内存。根据Fu等人[12]的传统LNS和浮点合成数据推断,QCLNS在13到45位的精度上平均节省了10%的FPGA资源。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Towards a Quaternion Complex Logarithmic Number System
The well-known generalization of real to complex arithmetic (two reals) extends further to more obscure quaternion arithmetic (four reals), which has applications in signal processing, aerospace, graphics and virtual reality. Quaternion multiplication implements 3D rotation, but is expensive (usually 16 floating-point multiplications and 12 additions). This paper proposes an alternative quaternion representation using logarithms to reduce multiplication cost. The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division in embedded and FPGA-based systems. Recent advances in the Complex LNS (CLNS) [5] have made fast log-polar complex representation affordable. Although the quaternion logarithm function is also well-defined, it is not useful to simplify multiplication (in the same way real and complex logarithms are) because quaternion multiplication is not commutative but quaternion addition is. To overcome this, we propose a novel Quaternion Complex (QCLNS) representation using a pair of CLNS numbers. This representation implements quaternion multiplication using only the theoretical minimum [11], [15] of 8 LNS multipliers (i.e., fixed-point adders) and two CLNS adders. Because CLNS numbers are more compact than ordinary rectangular complex representation, single-precision QCLNS occupies 10.9 percent less memory than conventional quaternion representation. Extrapolating conventional LNS and floating-point synthesis data from Fu et al. [12], QCLNS saves on average 10 percent of FPGA resources for precisions between 13 and 45 bits.
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