Cache Prefetching in Embedded DSPs

Prefetching has been a commonplace feature in the general purpose CPU world for more than a decade but has been much less common in the embedded and mobile world, moreover it has not been utilized for DSPs. The goal of this paper is to adapt and simulate straight-forward hardware prefetching techniques for embedded DSPs, assess their performance using the cycle count metric and find their potential improvement under the strict constraints of low power and low complexity. By using industry standard benchmarks we come to the conclusion that even though these algorithms exhibit a very high inherent hit rate, total cycle count improvement is possible due to relatively high external memory delay that stems from shared buses. Several parameters are simulated, including but not limited to cache size, number of prefetched blocks and the use of a small FIFO buffer to store the prefetched blocks as opposed to writing them directly into cache memory. We show that even a small FIFO buffer results in an improvement of 8% on average and up to 35% in total cycle count even in traces that exhibited a cache hit rate of over 99% without prefetching. We also show that a small prefetch buffer enables us to halve the cache size with no discernible effect on performance.