基于Intel Max 10 FPGA的1.8V/3.3V 100Mbps GPIO变送器设计

2022 IEEE Fourth International Conference on Advances in Electronics, Computers and Communications (ICAECC) Pub Date : 2022-01-10 DOI:10.1109/ICAECC54045.2022.9716630

Thati Sethu Sumanth, G.VenkataMallikarjjuna Reddy, A. Reddy

{"title":"基于Intel Max 10 FPGA的1.8V/3.3V 100Mbps GPIO变送器设计","authors":"Thati Sethu Sumanth, G.VenkataMallikarjjuna Reddy, A. Reddy","doi":"10.1109/ICAECC54045.2022.9716630","DOIUrl":null,"url":null,"abstract":"This paper presents the design of 1.8V/3.3V 100 Mbps General Purpose Input/Output (GPIO) transmitter for an Intel Max 10 FPGA. This transmitter works for both 1.8V and 3.3V IO supplies. The building blocks of this transmitter are level shifter and driver circuits. The level shifter is designed to level up the data levels from 0.8V to 1.8V/3.3V. A progressive sized driver circuit is designed to drive 50$\\Omega$ termination resistance and the load capacitance of 5pF as per the requirement of Intel Max10. The overall design is carried out with 22nm technology node on cadence virtuoso platform and is simulated across PVT. The simulation results shows that the proposed design supports up to a data rate of 100Mbps with a power consumption of 1.59mW at 1.8V supply and with a power consumption of 2.93mW at 3.3V supply.","PeriodicalId":199351,"journal":{"name":"2022 IEEE Fourth International Conference on Advances in Electronics, Computers and Communications (ICAECC)","volume":"10 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a 1.8V/3.3V 100Mbps GPIO Transmitter for Intel Max 10 FPGA\",\"authors\":\"Thati Sethu Sumanth, G.VenkataMallikarjjuna Reddy, A. Reddy\",\"doi\":\"10.1109/ICAECC54045.2022.9716630\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of 1.8V/3.3V 100 Mbps General Purpose Input/Output (GPIO) transmitter for an Intel Max 10 FPGA. This transmitter works for both 1.8V and 3.3V IO supplies. The building blocks of this transmitter are level shifter and driver circuits. The level shifter is designed to level up the data levels from 0.8V to 1.8V/3.3V. A progressive sized driver circuit is designed to drive 50$\\\\Omega$ termination resistance and the load capacitance of 5pF as per the requirement of Intel Max10. The overall design is carried out with 22nm technology node on cadence virtuoso platform and is simulated across PVT. The simulation results shows that the proposed design supports up to a data rate of 100Mbps with a power consumption of 1.59mW at 1.8V supply and with a power consumption of 2.93mW at 3.3V supply.\",\"PeriodicalId\":199351,\"journal\":{\"name\":\"2022 IEEE Fourth International Conference on Advances in Electronics, Computers and Communications (ICAECC)\",\"volume\":\"10 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Fourth International Conference on Advances in Electronics, Computers and Communications (ICAECC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAECC54045.2022.9716630\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Fourth International Conference on Advances in Electronics, Computers and Communications (ICAECC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAECC54045.2022.9716630","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文介绍了基于Intel Max 10 FPGA的1.8V/3.3V 100 Mbps通用输入/输出(GPIO)变送器的设计。此发射器适用于1.8V和3.3V IO电源。该发射机的组成部分是电平移位器和驱动电路。电平移位器设计用于将数据电平从0.8V调至1.8V/3.3V。根据Intel Max10的要求，设计了一种递进式驱动电路，以驱动50$\Omega$的终端电阻和5pF的负载电容。总体设计采用22nm技术节点在cadence virtuoso平台上进行，并在pvm上进行了仿真。仿真结果表明，所提出的设计在1.8V供电时支持高达100Mbps的数据速率，功耗为1.59mW，在3.3V供电时功耗为2.93mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design of a 1.8V/3.3V 100Mbps GPIO Transmitter for Intel Max 10 FPGA

This paper presents the design of 1.8V/3.3V 100 Mbps General Purpose Input/Output (GPIO) transmitter for an Intel Max 10 FPGA. This transmitter works for both 1.8V and 3.3V IO supplies. The building blocks of this transmitter are level shifter and driver circuits. The level shifter is designed to level up the data levels from 0.8V to 1.8V/3.3V. A progressive sized driver circuit is designed to drive 50$\Omega$ termination resistance and the load capacitance of 5pF as per the requirement of Intel Max10. The overall design is carried out with 22nm technology node on cadence virtuoso platform and is simulated across PVT. The simulation results shows that the proposed design supports up to a data rate of 100Mbps with a power consumption of 1.59mW at 1.8V supply and with a power consumption of 2.93mW at 3.3V supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2022 IEEE Fourth International Conference on Advances in Electronics, Computers and Communications (ICAECC)

自引率

0.00%

发文量