{"title":"研究复合半导体材料对SoC中漏极区扩展隧道晶体管的影响","authors":"Upasana, Hasti Kasundra, Mridula Gupta, M. Saxena","doi":"10.1109/EDKCON.2018.8770392","DOIUrl":null,"url":null,"abstract":"This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Studying the Impact of Compound Semiconductor Material in Drain Region Extended Tunnel Transistor for SoC Applications\",\"authors\":\"Upasana, Hasti Kasundra, Mridula Gupta, M. Saxena\",\"doi\":\"10.1109/EDKCON.2018.8770392\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.\",\"PeriodicalId\":344143,\"journal\":{\"name\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDKCON.2018.8770392\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770392","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Studying the Impact of Compound Semiconductor Material in Drain Region Extended Tunnel Transistor for SoC Applications
This work describes how conventional SOI-LDMOS has been converted into Drain Region Extended (DRE) Tunnel Transistor kind of structure by studying effects of various parameters that affects the device characteristics and modifying the device accordingly. Material-based study has been done in order to improvise the device functioning for System on Chip (SoC) applications in terms of higher breakdown and lower on-resistance.