Analysis of defects created at Si/SiO2 interface in a power RF LDMOS device due to temperature effects

Thermal constraints and the variation of high temperature levels are two of the most observed degradation mechanisms in power RF electronic devices. In order to evaluate the degradation level, the main indicator may be the measurement of on-state resistance (R$_{DS-on}$), which is systematically associated with the evolution of the internal device structure. This is a study of temperature effects on I-V characteristics of N-channel power RF LDMOS devices, and especially of RDS-on resistance; which is a main constraint of LDMOS devices in high temperature operations, that can partially or total change the performances of physical and electrical device. R$_{DS-on}$ has strong temperature dependence. The main parameters relevant to the temperature effects of the electrical characterization of the device is reported and proven by the basic physical behavior. The analysis of the experimental results is presented and the physical simulations (2D ATLAS–SILVACO) are used to explain and observe the physical preview of temperature impacts on power RF LDMOS performance. The physical parameters like current lines, concentration, electric field and mobility are taken into consideration follows temperature dependence. Finally, initial impacts analysis is discussed.