{"title":"可调谐近零阈值CMOS的高效32/spl倍/32位乘法器","authors":"V. Svilan, M. Matsui, J. Burr","doi":"10.1109/LPE.2000.155297","DOIUrl":null,"url":null,"abstract":"An 80,000 transistor, low swing, 32/spl times/32-bit multiplier was fabricated in a standard 0.35 /spl mu/m, V/sub th/=0.5 V CMOS process and in a 0.35 /spl mu/m, back-bias tunable, near-zero V/sub th/ process. While standard CMOS at V/sub dd/=3.3 V runs at 136 MHz, the same performance can be achieved in the low-V/sub th/ version at V/sub dd/=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-V/sub th/ version is able to run at 188 MHz, which is 38% faster than standard CMOS.","PeriodicalId":188020,"journal":{"name":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Energy-efficient 32/spl times/32-bit multiplier in tunable near-zero threshold CMOS\",\"authors\":\"V. Svilan, M. Matsui, J. Burr\",\"doi\":\"10.1109/LPE.2000.155297\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An 80,000 transistor, low swing, 32/spl times/32-bit multiplier was fabricated in a standard 0.35 /spl mu/m, V/sub th/=0.5 V CMOS process and in a 0.35 /spl mu/m, back-bias tunable, near-zero V/sub th/ process. While standard CMOS at V/sub dd/=3.3 V runs at 136 MHz, the same performance can be achieved in the low-V/sub th/ version at V/sub dd/=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-V/sub th/ version is able to run at 188 MHz, which is 38% faster than standard CMOS.\",\"PeriodicalId\":188020,\"journal\":{\"name\":\"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LPE.2000.155297\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LPE.2000.155297","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Energy-efficient 32/spl times/32-bit multiplier in tunable near-zero threshold CMOS
An 80,000 transistor, low swing, 32/spl times/32-bit multiplier was fabricated in a standard 0.35 /spl mu/m, V/sub th/=0.5 V CMOS process and in a 0.35 /spl mu/m, back-bias tunable, near-zero V/sub th/ process. While standard CMOS at V/sub dd/=3.3 V runs at 136 MHz, the same performance can be achieved in the low-V/sub th/ version at V/sub dd/=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-V/sub th/ version is able to run at 188 MHz, which is 38% faster than standard CMOS.
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