用于0.13 μm CMOS半导体激光器相干锁定的外差锁相环,采集范围为GHz

F. Aflatouni, O. Momeni, H. Hashemi
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引用次数: 7

摘要

提出了一种能够锁定半导体激光器频率和相位的外差电光锁相环结构。受射频图像抑制接收器和数字锁相环架构组合启发的辅助采集电路被集成到EOPLL中,即使在EOPLL中存在较大的光延迟的情况下,也可以将频率采集范围扩展到GHz。集成电路原型采用0.13 μm CMOS技术,包括宽带跨阻放大器和锁相环电路。本文报道了独立芯片的测量结果和使用该芯片的垂直腔面发射激光器(VCSEL)的锁定。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A heterodyne phase locked loop with GHz acquisition range for coherent locking of semiconductor lasers in 0.13 μm CMOS
A heterodyne electro-optical phase locked loop (EO-PLL) architecture is proposed that can lock the frequency and phase of semiconductor lasers. An aided acquisition circuit inspired by the combination of RF image rejection receivers and digital PLL architectures is incorporated in the EOPLL to extend the frequency acquisition range to GHz, even in the presence of large optical delays in the EOPLL. An integrated circuit prototype is implemented in a 0.13 μm CMOS technology and includes a wide bandwidth transimpedance amplifier and the PLL circuitry. Measurement results for the stand-alone chip and the locking of vertical cavity surface emitting lasers (VCSEL) using the implemented chip are reported.
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