{"title":"宽带ISDN中基于共享缓冲的ATM交换机设计","authors":"S. Kumar, D. Agrawal","doi":"10.1109/PCCC.1994.504141","DOIUrl":null,"url":null,"abstract":"This paper presents a shared buffer ATM switch architecture suitable for broadband integrated services digital networks. This switch mainly consists of 1K ATM-cell memory, a corresponding routing tag memory, two independent but cooperating memory control units along with associated multiplexers/demultiplexers and serial/parallel converters. The proposed shared-buffer switch architecture exploits the parallelization of memory operations required to perform efficient ATM switching with increased ATM cell processing time. A concept of switching efficiency at the hardware level namely, the switching-slot efliciency for a shared buffer ATM switch has been introduced. A design to enhance the switching slot efficiency of a shared buffer ATM switch by parallelizing memory operations within the switch has been proposed. Kevwords ATM switching, B-ISDN, performance evaluation, shared-buffer architecture, switching efficiency.","PeriodicalId":203232,"journal":{"name":"Proceeding of 13th IEEE Annual International Phoenix Conference on Computers and Communications","volume":"195 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"On Design of a Shared-Buffer based ATM Switch for Broadband ISDN\",\"authors\":\"S. Kumar, D. Agrawal\",\"doi\":\"10.1109/PCCC.1994.504141\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a shared buffer ATM switch architecture suitable for broadband integrated services digital networks. This switch mainly consists of 1K ATM-cell memory, a corresponding routing tag memory, two independent but cooperating memory control units along with associated multiplexers/demultiplexers and serial/parallel converters. The proposed shared-buffer switch architecture exploits the parallelization of memory operations required to perform efficient ATM switching with increased ATM cell processing time. A concept of switching efficiency at the hardware level namely, the switching-slot efliciency for a shared buffer ATM switch has been introduced. A design to enhance the switching slot efficiency of a shared buffer ATM switch by parallelizing memory operations within the switch has been proposed. Kevwords ATM switching, B-ISDN, performance evaluation, shared-buffer architecture, switching efficiency.\",\"PeriodicalId\":203232,\"journal\":{\"name\":\"Proceeding of 13th IEEE Annual International Phoenix Conference on Computers and Communications\",\"volume\":\"195 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-04-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceeding of 13th IEEE Annual International Phoenix Conference on Computers and Communications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PCCC.1994.504141\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceeding of 13th IEEE Annual International Phoenix Conference on Computers and Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PCCC.1994.504141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On Design of a Shared-Buffer based ATM Switch for Broadband ISDN
This paper presents a shared buffer ATM switch architecture suitable for broadband integrated services digital networks. This switch mainly consists of 1K ATM-cell memory, a corresponding routing tag memory, two independent but cooperating memory control units along with associated multiplexers/demultiplexers and serial/parallel converters. The proposed shared-buffer switch architecture exploits the parallelization of memory operations required to perform efficient ATM switching with increased ATM cell processing time. A concept of switching efficiency at the hardware level namely, the switching-slot efliciency for a shared buffer ATM switch has been introduced. A design to enhance the switching slot efficiency of a shared buffer ATM switch by parallelizing memory operations within the switch has been proposed. Kevwords ATM switching, B-ISDN, performance evaluation, shared-buffer architecture, switching efficiency.
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