各种全加法器电路的节奏分析

2015 International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT) Pub Date : 2015-01-12 DOI:10.1109/ERECT.2015.7498994

K. Manjunath, P. S. Abdul Lateef Haroon, A. Pagi, J. Ulaganathan

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引用次数: 14

摘要

加法器是任何处理器/控制器设计中的重要组成部分。迄今为止，已经提出和设计了大量的1位全加法器电路。在本文中，我们对各种全加法器电路进行了分析和比较描述，考虑了功耗、运算速度和面积等各种约束条件。电路是在virtuoso平台上设计的，使用cadence工具和可用的GPDK - 45nm套件。成功地设计了最多28个晶体管的Fulladder电路和只有6个晶体管的Fulladder电路，并对功耗、运行速度(延迟)和面积(晶体管数)等各种参数进行了模拟和比较，最终得出了适合特定规格的最佳设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of various full-adder circuits in cadence

The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using cadence tool with the available GPDK - 45nm kit. The Fulladder circuits with the most 28 transistor to the one with only 6 transistors are successfully designed, simulated and compared for various parameters like power consumption, speed of operation(delay) and area (transistor count), and finally concluded the best designs, that suite for the particular specifications.

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2015 International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)

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