{"title":"基于65nm CMOS技术的低压逆变器连续时间σ δ模数转换器","authors":"A. Essawy, A. Ismail","doi":"10.1109/FTFC.2014.6828599","DOIUrl":null,"url":null,"abstract":"In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply in 65 nm CMOS technology.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A low voltage inverter-based continuous-time sigma delta analog-to-digital converter in 65nm CMOS technology\",\"authors\":\"A. Essawy, A. Ismail\",\"doi\":\"10.1109/FTFC.2014.6828599\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply in 65 nm CMOS technology.\",\"PeriodicalId\":138166,\"journal\":{\"name\":\"2014 IEEE Faible Tension Faible Consommation\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Faible Tension Faible Consommation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FTFC.2014.6828599\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Faible Tension Faible Consommation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTFC.2014.6828599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
在这项工作中，提出了一种基于逆变的低压实现连续时间σ δ模数转换器。提出的实现应用于三阶单环路调制器。环路滤波器采用有源RC积分器实现。在65纳米CMOS技术中，信号带宽为2 MHz，采样频率为100 MHz，同时从0.75 V电源消耗1 mA，实现了50 dB SNDR。
A low voltage inverter-based continuous-time sigma delta analog-to-digital converter in 65nm CMOS technology
In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply in 65 nm CMOS technology.
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