Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan
{"title":"55mm /sup 2/ 256mb NROM闪存,内置微控制器,采用基于NROM的程序文件ROM","authors":"Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan","doi":"10.1109/ISSCC.2004.1332587","DOIUrl":null,"url":null,"abstract":"A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.","PeriodicalId":273317,"journal":{"name":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 55 mm/sup 2/ 256 Mb NROM flash memory with embedded microcontroller using an NROM-based program file ROM\",\"authors\":\"Y. Sofer, M. Edan, Y. Betser, M. Grossgold, E. Maayan, B. Eitan\",\"doi\":\"10.1109/ISSCC.2004.1332587\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.\",\"PeriodicalId\":273317,\"journal\":{\"name\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2004.1332587\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2004.1332587","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 55 mm/sup 2/ 256 Mb NROM flash memory with embedded microcontroller using an NROM-based program file ROM
A 256 Mb flash memory based on 2 b/cell 0.17 /spl mu/m NROM technology supports 90 ns random read access, 66 MHz synchronous read, and 3 /spl mu/s/word programming. This 55 mm/sup 2/ device includes an 8 b embedded microcontroller for program and erase operations, power-up sequence, BIST, and more. The microcontroller executes its code from an NROM-based embedded ROM, performing 30 ns/word read access.