800兆赫信号传输时数据总线上DRAM输入阻抗(Lin,Cin,Rin)的最佳窗口

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824122

Ki-Whan Song, K. Kyung, Changhyun Kim

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引用次数: 2

摘要

本文介绍了一种分析长周期信道的方法。这项工作是针对RAMBUS系统进行的。重点分析了DRAM加载对电信号完整性的影响。我们提出了一些适合800 MHz信号的DRAM输入阻抗窗口。如果没有对/spl Delta/Lin的额外约束(引脚对引脚的Lin差异)，则偏度为45 ps，通过在1.5 nH内控制/spl Delta/Lin可以将其降低到22 ps。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Optimum windows of DRAM input impedance (Lin,Cin,Rin) on data bus for 800 MHz signaling

This paper describes a methodology to analyze a long periodic channel. The work was performed for the RAMBUS system. The analysis is focused on DRAM loading effects on electrical signal integrity. We suggest some proper windows of DRAM input impedance for 800 MHz signaling. Without additional constraints to /spl Delta/Lin (pin-to-pin Lin differences), the skew amounts to 45 ps, which can be lowered to 22 ps by the control of /spl Delta/Lin within 1.5 nH.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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