High level characterization and optimization of a GPSK modulator with genetic algorithm

Today, design requirements are extending more and more from electronic (analogue and digital) to multidiscipline ones. These current needs imply implementation of methodologies to make the CAD product reliable in order to improve time to market, study costs, reusability and reliability of the design process. This paper proposes a high level design approach applied for the characterization and the optimization of fractional-N synthesizer acting as a direct GPSK modulator and designed for the UMTS standard application. It uses the hardware description language VHDL-AMS and a genetic algorithm to optimize the modulator with a considerably reduced CPU time before passing to a transistor level characterization.