{"title":"故障分级运行自检","authors":"R.T. Aparicio, P. Hallinan","doi":"10.1109/ASIC.1989.123221","DOIUrl":null,"url":null,"abstract":"A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today's CAE tools. A fault simulation methodology and design guidelines for optimizing the fault grading performance on these large systems are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fault grading operational self-test\",\"authors\":\"R.T. Aparicio, P. Hallinan\",\"doi\":\"10.1109/ASIC.1989.123221\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today's CAE tools. A fault simulation methodology and design guidelines for optimizing the fault grading performance on these large systems are discussed.<<ETX>>\",\"PeriodicalId\":245997,\"journal\":{\"name\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1989.123221\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123221","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today's CAE tools. A fault simulation methodology and design guidelines for optimizing the fault grading performance on these large systems are discussed.<>
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