可扩展到VLIW架构的可配置媒体嵌入式处理器的设计方法和系统

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 2002-09-16 DOI:10.1109/ICCD.2002.1106738

Atsushi Mizuno, K. Kohno, Ryuichiro Ohyama, T. Tokuyoshi, H. Uetani, H. Eichel, T. Miyamori, Nobu Matsumoto, M. Matsui

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引用次数: 35

摘要

开发了一种用于多媒体应用的可配置嵌入式处理器设计和生成的集成系统。该系统“媒体嵌入式处理器集成器”提供了一个独特的功能，不仅为可配置嵌入式处理器，而且为其基于模板的可扩展VLIW协处理器生成编译器和模拟器等开发工具。本文介绍了“媒体嵌入式处理器集成器”的体系结构和功能，重点介绍了该系统如何处理VLIW协处理器扩展。为了确定用于图像识别的3路VLIW协处理器的ISA，以系统生成的相应编译器和模拟器为例，对几种不同的ISA进行了评估和比较，以获得最佳性能。该系统极大地减少了整个ISA定义过程。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design methodology and system for a configurable media embedded processor extensible to VLIW architecture

A new integrated system to design and generate a configurable embedded processor for multimedia applications has been developed. The system, "Media embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable embedded processor but also for its template based extensible VLIW co-processor. This paper describes the architecture and the function of the "Media embedded Processor Integrator" especially focusing on how the system treats the VLIW co-processor extension. In order to determine an ISA for a 3-way VLIW co-processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.

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来源期刊

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

CiteScore

2.30

自引率

0.00%

发文量