{"title":"计算系统实现的算法和架构","authors":"L. Carro, A. Suzim","doi":"10.1109/IWRSP.1994.315893","DOIUrl":null,"url":null,"abstract":"This paper describes some techniques currently under research to explore hardware-software tradeoffs during a system development. We show that the moving of SW operations to HW can be further improved if the source code is modified in order to increase the overall parallelism of the system. We then show the limits of this approach and a new RISC architecture under research to overcome this limitations.<<ETX>>","PeriodicalId":261113,"journal":{"name":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Algorithms and architectures to computational systems implementation\",\"authors\":\"L. Carro, A. Suzim\",\"doi\":\"10.1109/IWRSP.1994.315893\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes some techniques currently under research to explore hardware-software tradeoffs during a system development. We show that the moving of SW operations to HW can be further improved if the source code is modified in order to increase the overall parallelism of the system. We then show the limits of this approach and a new RISC architecture under research to overcome this limitations.<<ETX>>\",\"PeriodicalId\":261113,\"journal\":{\"name\":\"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWRSP.1994.315893\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 5th International Workshop on Rapid System Prototyping","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWRSP.1994.315893","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Algorithms and architectures to computational systems implementation
This paper describes some techniques currently under research to explore hardware-software tradeoffs during a system development. We show that the moving of SW operations to HW can be further improved if the source code is modified in order to increase the overall parallelism of the system. We then show the limits of this approach and a new RISC architecture under research to overcome this limitations.<>