基于fpga的HIPERLAN/2基4蝴蝶

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) Pub Date : 2002-08-07 DOI:10.1109/ISCAS.2002.1010214

A. Pérez-Pascual, T. Sansaloni, J. Valls-Coquillat

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引用次数: 15

摘要

本文介绍了两种适用于HIPERLAN 2的基数-4蝴蝶的fpga实现方法。这两种方法可以有效地利用目标设备中可用的硬件资源，并且减少了相对于直接实现基数-4蝴蝶的面积。这两种方法都减少了存储系数所需的面积。第一种是利用系数的对称性来减少需要存储的函数的数量;第二种是利用嵌入式块ram的双端口能力。

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FPGA-based radix-4 butterflies for HIPERLAN/2

This paper presents two different FPGA-implementation of radix-4 butterflies suitable for HIPERLAN 2. The two approaches lead to an efficient use of the hardware resources available in the target device and reduces the area with respect to the direct implementation of the radix-4 butterfly. Both methods reduce the area required storing the coefficients. The first one uses the symmetries of coefficients for reducing the number of functions to store; the second one takes advantage of the dual-port capability of the embedded block-RAM.

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来源期刊

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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