{"title":"350-MHz组合TDC-DTC，分辨率为61 ps，适用于异步ΔΣ ADC应用","authors":"J. Daniels, W. Dehaene, M. Steyaert, A. Wiesbauer","doi":"10.1109/ASSCC.2008.4708803","DOIUrl":null,"url":null,"abstract":"A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 350-MHz combined TDC-DTC With 61 ps resolution for asynchronous ΔΣ ADC applications\",\"authors\":\"J. Daniels, W. Dehaene, M. Steyaert, A. Wiesbauer\",\"doi\":\"10.1109/ASSCC.2008.4708803\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708803\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708803","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 350-MHz combined TDC-DTC With 61 ps resolution for asynchronous ΔΣ ADC applications
A combined Time-to-Digital Digital-to-Time Converter (TDC-DTC) is presented for use in a high-precision single-bit Asynchronous DeltaSigma ADC. It quantizes the 1-bit asynchronous square wave with 61 ps precision, obtaining a virtual sampling frequency of 16.4 GHz with only a 350 MHz clock. Measurements confirm that with this precision, the design of a single-bit Asynchronous DeltaSigma ADC obtaining 78 dB SNDR over a 500 kHz bandwidth is feasible using only a first-order noise shaping and with a limit cycle frequency of only 8 MHz. With this technique, both the order and the bandwidth requirements of the noise shaping filter can be relaxed, which significantly reduces the analog complexity of the DeltaSigma Modulator. The proposed architecture is therefore especially suited for low-voltage nanometer technologies.
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