{"title":"基于LVDS驱动的高速串行链路CMOS变送器设计","authors":"Wonki Park, Sungmin Lee","doi":"10.1109/ICEIE.2010.5559870","DOIUrl":null,"url":null,"abstract":"This paper presents a low-power CMOS multichannel transmitter that achieves a data rate of 3.125Gb/s/ch. The LVDS (Low-voltage differential-signaling) driver is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. The prototype chip is comprised of 4 channels and was fabricated in a 0.18 μm standard CMOS process. The measured output jitter of transmitter is 100ps, peak-to-peak(0.31UI). The area of the chip is 0.045 mm2 and the power consumption is about 48mW/ch.","PeriodicalId":211301,"journal":{"name":"2010 International Conference on Electronics and Information Engineering","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Design of LVDS driver based CMOS transmitter for a high speed serial link\",\"authors\":\"Wonki Park, Sungmin Lee\",\"doi\":\"10.1109/ICEIE.2010.5559870\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low-power CMOS multichannel transmitter that achieves a data rate of 3.125Gb/s/ch. The LVDS (Low-voltage differential-signaling) driver is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. The prototype chip is comprised of 4 channels and was fabricated in a 0.18 μm standard CMOS process. The measured output jitter of transmitter is 100ps, peak-to-peak(0.31UI). The area of the chip is 0.045 mm2 and the power consumption is about 48mW/ch.\",\"PeriodicalId\":211301,\"journal\":{\"name\":\"2010 International Conference on Electronics and Information Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Conference on Electronics and Information Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEIE.2010.5559870\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Electronics and Information Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEIE.2010.5559870","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of LVDS driver based CMOS transmitter for a high speed serial link
This paper presents a low-power CMOS multichannel transmitter that achieves a data rate of 3.125Gb/s/ch. The LVDS (Low-voltage differential-signaling) driver is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. The prototype chip is comprised of 4 channels and was fabricated in a 0.18 μm standard CMOS process. The measured output jitter of transmitter is 100ps, peak-to-peak(0.31UI). The area of the chip is 0.045 mm2 and the power consumption is about 48mW/ch.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
