TRL电路传播延迟分析

AIEE-ACM-IRE '58 (Eastern) Pub Date : 1958-12-03 DOI:10.1145/1458043.1458066

W. Dunnet, E. P. Auger, A. Scott

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引用次数: 4

摘要

摘要:目前正在Sylvania数据处理实验室进行一个程序，设计晶体管-电阻逻辑(TRL)电路并在数字计算机上编译TRL传播延迟表。本文指出了这样一个程序的必要性，并描述了晶体管和TRL电路的研究，这些研究已经导致了基本关系的编程。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of TRL circuit propagation delay

Synopsis: A program to design transistor-resistor logic (TRL) circuits and compile TRL propagation delay tables on a digital computer is presently underway at the Sylvania Data Processing Laboratory. This paper points to the need for such a program and describes transistor and TRL circuit studies that have resulted in the basic relationships being programmed.

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来源期刊

AIEE-ACM-IRE '58 (Eastern)

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