采用亚16nm块体FinFET技术的位线边缘传感技术，实现了一种128 kb 10%功耗降低的1T高密度ROM，访问时间为0.56 ns

2015 28th IEEE International System-on-Chip Conference (SOCC) Pub Date : 2015-09-01 DOI:10.1109/SOCC.2015.7406972

Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev K. Jain

{"title":"采用亚16nm块体FinFET技术的位线边缘传感技术，实现了一种128 kb 10%功耗降低的1T高密度ROM，访问时间为0.56 ns","authors":"Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev K. Jain","doi":"10.1109/SOCC.2015.7406972","DOIUrl":null,"url":null,"abstract":"A 128-kb 1T High Density read only memory (ROM) with 256 bitcells per bitline is implemented in sub 16nm bulk FinFET process. A novel high speed single ended bitline edge sensing scheme is presented using a diode based level detector as sense amplifier. The 128-kb ROM macro realizes a 0.56 ns read access time at 0.85 V, with an average improvement of 20% over conventional ROM macro using the single ended inverter sensing scheme. Dynamic power dissipation is reduced by 10% with no silicon area overhead as compared to conventional ROM macro.","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology\",\"authors\":\"Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev K. Jain\",\"doi\":\"10.1109/SOCC.2015.7406972\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 128-kb 1T High Density read only memory (ROM) with 256 bitcells per bitline is implemented in sub 16nm bulk FinFET process. A novel high speed single ended bitline edge sensing scheme is presented using a diode based level detector as sense amplifier. The 128-kb ROM macro realizes a 0.56 ns read access time at 0.85 V, with an average improvement of 20% over conventional ROM macro using the single ended inverter sensing scheme. Dynamic power dissipation is reduced by 10% with no silicon area overhead as compared to conventional ROM macro.\",\"PeriodicalId\":329464,\"journal\":{\"name\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2015.7406972\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2015.7406972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

采用亚16nm批量FinFET工艺实现了128kb的1T高密度只读存储器(ROM)，每位行256位单元。提出了一种基于二极管的电平检测器作为感测放大器的高速单端位线边缘检测方案。128 kb ROM宏在0.85 V下实现了0.56 ns的读取访问时间，比使用单端逆变器传感方案的传统ROM宏平均提高了20%。与传统的ROM宏相比，动态功耗降低了10%，没有硅面积开销。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology

A 128-kb 1T High Density read only memory (ROM) with 256 bitcells per bitline is implemented in sub 16nm bulk FinFET process. A novel high speed single ended bitline edge sensing scheme is presented using a diode based level detector as sense amplifier. The 128-kb ROM macro realizes a 0.56 ns read access time at 0.85 V, with an average improvement of 20% over conventional ROM macro using the single ended inverter sensing scheme. Dynamic power dissipation is reduced by 10% with no silicon area overhead as compared to conventional ROM macro.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 28th IEEE International System-on-Chip Conference (SOCC)

自引率

0.00%

发文量