{"title":"基于CTRON内核的GMICRO/500微处理器性能评价","authors":"M. Yamamoto, I. Kawasaki, Y. Fuzino, H. Taguchi","doi":"10.1109/TRON.1993.589171","DOIUrl":null,"url":null,"abstract":"The GMICRO/500 is a high-performance 32-b microprocessor based on the TRON specification. The authors evaluate the performance of the GMICRO/500 under the CTRON based OS environment. They developed an evaluation system for the CTRON based kernel interface to evaluate the execution time of each system call under the several conditions. The authors applied this evaluation system to GMICRO/500 and GMICRO/300 processors. The performance of the GMICRO/500 which is measured with a behavior model simulator, and compared with the performance of the GMICRO/300 which is measured with a real machine. An advantage of the GMICRO/500's superscalar architecture is most derived when it operates with a secondary cache.","PeriodicalId":134393,"journal":{"name":"Proceedings the Tenth Project International Symposium, 1993","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Performance evaluation of GMICRO/500 microprocessor for CTRON based kernel\",\"authors\":\"M. Yamamoto, I. Kawasaki, Y. Fuzino, H. Taguchi\",\"doi\":\"10.1109/TRON.1993.589171\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The GMICRO/500 is a high-performance 32-b microprocessor based on the TRON specification. The authors evaluate the performance of the GMICRO/500 under the CTRON based OS environment. They developed an evaluation system for the CTRON based kernel interface to evaluate the execution time of each system call under the several conditions. The authors applied this evaluation system to GMICRO/500 and GMICRO/300 processors. The performance of the GMICRO/500 which is measured with a behavior model simulator, and compared with the performance of the GMICRO/300 which is measured with a real machine. An advantage of the GMICRO/500's superscalar architecture is most derived when it operates with a secondary cache.\",\"PeriodicalId\":134393,\"journal\":{\"name\":\"Proceedings the Tenth Project International Symposium, 1993\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings the Tenth Project International Symposium, 1993\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TRON.1993.589171\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings the Tenth Project International Symposium, 1993","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TRON.1993.589171","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance evaluation of GMICRO/500 microprocessor for CTRON based kernel
The GMICRO/500 is a high-performance 32-b microprocessor based on the TRON specification. The authors evaluate the performance of the GMICRO/500 under the CTRON based OS environment. They developed an evaluation system for the CTRON based kernel interface to evaluate the execution time of each system call under the several conditions. The authors applied this evaluation system to GMICRO/500 and GMICRO/300 processors. The performance of the GMICRO/500 which is measured with a behavior model simulator, and compared with the performance of the GMICRO/300 which is measured with a real machine. An advantage of the GMICRO/500's superscalar architecture is most derived when it operates with a secondary cache.
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