I. Basith, Tareq Muhammad Supon, Ajit Muhury, R. Rashidzadeh, M. Ahmadi
{"title":"单电子结1位全加法器的性能增强","authors":"I. Basith, Tareq Muhammad Supon, Ajit Muhury, R. Rashidzadeh, M. Ahmadi","doi":"10.1109/ICECS.2011.6122238","DOIUrl":null,"url":null,"abstract":"The focus of this paper is to study the reliability issue of single-electron tunneling (SET) technology using multi-island structure for 1-bit full adder circuit. A new set of parameters are proposed in this paper showing better sensitivity towards the random background charge (RBC). Impact of temperature and background charge on the performance parameters and voltage swing are also analyzed. Multi-island clique (K-3) structure is implemented and compared with the designs reported in the literature.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Performance enhancement of single electron junction 1-bit full adder\",\"authors\":\"I. Basith, Tareq Muhammad Supon, Ajit Muhury, R. Rashidzadeh, M. Ahmadi\",\"doi\":\"10.1109/ICECS.2011.6122238\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The focus of this paper is to study the reliability issue of single-electron tunneling (SET) technology using multi-island structure for 1-bit full adder circuit. A new set of parameters are proposed in this paper showing better sensitivity towards the random background charge (RBC). Impact of temperature and background charge on the performance parameters and voltage swing are also analyzed. Multi-island clique (K-3) structure is implemented and compared with the designs reported in the literature.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122238\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance enhancement of single electron junction 1-bit full adder
The focus of this paper is to study the reliability issue of single-electron tunneling (SET) technology using multi-island structure for 1-bit full adder circuit. A new set of parameters are proposed in this paper showing better sensitivity towards the random background charge (RBC). Impact of temperature and background charge on the performance parameters and voltage swing are also analyzed. Multi-island clique (K-3) structure is implemented and compared with the designs reported in the literature.