Y. Ando, A. Wakejima, I. Miura, W. Contrata, H. Miyamoto, N. Samoto
{"title":"InAs/GaAs梯度超晶格通道晶体管(GSTs)","authors":"Y. Ando, A. Wakejima, I. Miura, W. Contrata, H. Miyamoto, N. Samoto","doi":"10.1109/DRC.1995.496241","DOIUrl":null,"url":null,"abstract":"Pseudomorphic high electron mobility transistors (PHEMTs) offer superior power and noise performances compared to conventional HEMTs. However, as gate voltage increases, PHEMTs still suffer from parallel conduction of electrons in doped AlGaAs. This effect not only decreases transconductance (g/sub m/) at high gate bias but also degrades power gain and efficiency for large-signal operation. High indium content channel would allow an increase in conduction band offset, and hence, suppression of the parallel conduction, but due to the lattice mismatch, the reliability of the device might be affected, and therefore, the maximum allowable InAs mole fraction is limited. In this paper, we propose a graded superlattice channel transistor (GST), which reduces parallel conduction while suppressing an increase of strain in the channel.","PeriodicalId":326645,"journal":{"name":"1995 53rd Annual Device Research Conference Digest","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"InAs/GaAs graded superlattice channel transistors (GSTs)\",\"authors\":\"Y. Ando, A. Wakejima, I. Miura, W. Contrata, H. Miyamoto, N. Samoto\",\"doi\":\"10.1109/DRC.1995.496241\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Pseudomorphic high electron mobility transistors (PHEMTs) offer superior power and noise performances compared to conventional HEMTs. However, as gate voltage increases, PHEMTs still suffer from parallel conduction of electrons in doped AlGaAs. This effect not only decreases transconductance (g/sub m/) at high gate bias but also degrades power gain and efficiency for large-signal operation. High indium content channel would allow an increase in conduction band offset, and hence, suppression of the parallel conduction, but due to the lattice mismatch, the reliability of the device might be affected, and therefore, the maximum allowable InAs mole fraction is limited. In this paper, we propose a graded superlattice channel transistor (GST), which reduces parallel conduction while suppressing an increase of strain in the channel.\",\"PeriodicalId\":326645,\"journal\":{\"name\":\"1995 53rd Annual Device Research Conference Digest\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 53rd Annual Device Research Conference Digest\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.1995.496241\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 53rd Annual Device Research Conference Digest","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1995.496241","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pseudomorphic high electron mobility transistors (PHEMTs) offer superior power and noise performances compared to conventional HEMTs. However, as gate voltage increases, PHEMTs still suffer from parallel conduction of electrons in doped AlGaAs. This effect not only decreases transconductance (g/sub m/) at high gate bias but also degrades power gain and efficiency for large-signal operation. High indium content channel would allow an increase in conduction band offset, and hence, suppression of the parallel conduction, but due to the lattice mismatch, the reliability of the device might be affected, and therefore, the maximum allowable InAs mole fraction is limited. In this paper, we propose a graded superlattice channel transistor (GST), which reduces parallel conduction while suppressing an increase of strain in the channel.