High-Speed Continuous Time Digitizer Using a Two-Level Multiphase Sampling Technique

In this paper, the new architecture of a high-speed continuous time digitizer has been proposed. With the aid of a two-level multiphase sampling technique, the time digitizer can use only 16 delay cells and DFFs to perform the flash-type conversion of 64-stage interpolation. The time digitizer can obtain 78 ps resolution with a reference frequency running at 200 MHz. The continuous input clock frequency can be up to 250 MHz. The layout area occupies 1.08 mm2. A novel clock multiplier is also introduced to provide multiphase generation with frequency output range within 640 MHz ~1.8 GHz.