多数表决VLSI的可靠性、可测试性和良率

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186155

C. Stroud, A. Barbour

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引用次数: 5

摘要

建立了采用多数投票技术确定超大规模集成电路设计可靠性和良率的数学模型。预测了显著的可靠性和良率改进，并与实际的VLSI实现进行了比较。通过满足可测试性条件，实现了容错和容错的统一方法。

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Reliability, testability and yield of majority voting VLSI

Mathematical models for determining the reliability and yield of VLSI designs incorporating majority voting techniques are developed. Significant reliability and yield improvements are predicted and compared to actual VLSI implementations. By satisfying testability conditions, a unified approach to fault and defect tolerance is achieved.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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