{"title":"采用QSD数字系统的快速免进位加法器设计","authors":"A. Awwal, J. U. Ahmed","doi":"10.1109/NAECON.1993.290791","DOIUrl":null,"url":null,"abstract":"A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided.<<ETX>>","PeriodicalId":183796,"journal":{"name":"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Fast carry free adder design using QSD number system\",\"authors\":\"A. Awwal, J. U. Ahmed\",\"doi\":\"10.1109/NAECON.1993.290791\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided.<<ETX>>\",\"PeriodicalId\":183796,\"journal\":{\"name\":\"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.1993.290791\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 1993 National Aerospace and Electronics Conference-NAECON 1993","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.1993.290791","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast carry free adder design using QSD number system
A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided.<>