改进了共享内存多处理器上的并行架构模拟

P. Konas, P. Yew
{"title":"改进了共享内存多处理器上的并行架构模拟","authors":"P. Konas, P. Yew","doi":"10.1145/182478.182584","DOIUrl":null,"url":null,"abstract":"In recent years, advances in technology and in the area of computer architecture have resulted in increasingly more complex designs. As the complexity of the designs increases, simulation becomes the only viable method for gaining insight into the operation of new as well as existing computer systems. One way to meet the excessive processing requirements of detailed computer systems simulations is to execute them on a multiprocessor machine. Computer systems simulations are inherently synchronous and contain significant amounts of inherent parallelism [8]. Hence, the main problem in such simulations is to exploit the available parelelism with the least possible overhead. Unfortunately, both conservative and optimistic asynchronous methods are not appropriate for such simulations because they introduce significant overheads in their attempt to find parallelism [8]. Therefore, we focus our attention on synchronous parallel simulation methods. In this paper we present a synchronous, parallel, event-driven approach (SPSDES). It differs from previous approaches in many ways: (1) it contains a single, global synchronization operation per simulation phase; (2) it introduces a minimum number of kernel operations into the simulation; (3) it allows for efficient processor self-scheduling; and (4) it aggressively exposes parallelism only when a simulation phase does not contain enough parallelism for the processors to exploit. We study the performance of SPaDES by simulating a symmetric multiprocessor (tat-get machine) on a NUMA multiprocessor (hosl machine). The NUMA characteristics of the host machine enable us to study the performance of the method under demanding run-time conditions and to assess the impact of partitioning and scheduling on the efficiency of the parallel simulator. The few kernel operations introduced by SPaDES, the use of a single barrier during each phase, and the exploitation of coarse-grain parallelism are the main reasons SPaDES achieves high performance. Our main concern in this paper is the performance of the proposed method in the simulation of synchronous architectural designs. In Section 2 we present the SPaDES simulation method, and in Section 3 we study its performance, Section 4 contains our conclusions and future research directions.","PeriodicalId":194781,"journal":{"name":"Workshop on Parallel and Distributed Simulation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Improved parallel architectural simulations on shared-memory multiprocessors\",\"authors\":\"P. Konas, P. Yew\",\"doi\":\"10.1145/182478.182584\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In recent years, advances in technology and in the area of computer architecture have resulted in increasingly more complex designs. As the complexity of the designs increases, simulation becomes the only viable method for gaining insight into the operation of new as well as existing computer systems. One way to meet the excessive processing requirements of detailed computer systems simulations is to execute them on a multiprocessor machine. Computer systems simulations are inherently synchronous and contain significant amounts of inherent parallelism [8]. Hence, the main problem in such simulations is to exploit the available parelelism with the least possible overhead. Unfortunately, both conservative and optimistic asynchronous methods are not appropriate for such simulations because they introduce significant overheads in their attempt to find parallelism [8]. Therefore, we focus our attention on synchronous parallel simulation methods. In this paper we present a synchronous, parallel, event-driven approach (SPSDES). It differs from previous approaches in many ways: (1) it contains a single, global synchronization operation per simulation phase; (2) it introduces a minimum number of kernel operations into the simulation; (3) it allows for efficient processor self-scheduling; and (4) it aggressively exposes parallelism only when a simulation phase does not contain enough parallelism for the processors to exploit. We study the performance of SPaDES by simulating a symmetric multiprocessor (tat-get machine) on a NUMA multiprocessor (hosl machine). The NUMA characteristics of the host machine enable us to study the performance of the method under demanding run-time conditions and to assess the impact of partitioning and scheduling on the efficiency of the parallel simulator. The few kernel operations introduced by SPaDES, the use of a single barrier during each phase, and the exploitation of coarse-grain parallelism are the main reasons SPaDES achieves high performance. Our main concern in this paper is the performance of the proposed method in the simulation of synchronous architectural designs. In Section 2 we present the SPaDES simulation method, and in Section 3 we study its performance, Section 4 contains our conclusions and future research directions.\",\"PeriodicalId\":194781,\"journal\":{\"name\":\"Workshop on Parallel and Distributed Simulation\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Workshop on Parallel and Distributed Simulation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/182478.182584\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Workshop on Parallel and Distributed Simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/182478.182584","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

近年来,技术和计算机体系结构领域的进步导致了越来越复杂的设计。随着设计复杂性的增加,模拟成为唯一可行的方法来获得洞察新的以及现有的计算机系统的操作。满足详细计算机系统模拟的过多处理要求的一种方法是在多处理器机器上执行它们。计算机系统模拟本质上是同步的,并且包含大量的固有并行性[8]。因此,这种模拟中的主要问题是在尽可能少的开销下利用可用的并行性。不幸的是,保守和乐观异步方法都不适合这种模拟,因为它们在尝试寻找并行性时引入了显著的开销[8]。因此,同步并行仿真方法成为我们关注的焦点。在本文中,我们提出了一种同步、并行、事件驱动的方法(SPSDES)。它在许多方面与以前的方法不同:(1)它在每个模拟阶段包含一个单一的全局同步操作;(2)在仿真中引入最少数量的内核操作;(3)允许高效的处理器自调度;(4)只有当模拟阶段没有包含足够的并行性供处理器利用时,它才会积极地暴露并行性。我们通过在NUMA多处理器(hosl机)上模拟对称多处理器(目标机)来研究SPaDES的性能。主机的NUMA特性使我们能够研究该方法在苛刻的运行条件下的性能,并评估分区和调度对并行模拟器效率的影响。SPaDES引入的少量内核操作、在每个阶段使用单个屏障以及对粗粒度并行性的利用是SPaDES实现高性能的主要原因。本文主要关注的是所提出的方法在同步架构设计仿真中的性能。第2节给出了SPaDES的仿真方法,第3节对其性能进行了研究,第4节给出了我们的结论和未来的研究方向。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Improved parallel architectural simulations on shared-memory multiprocessors
In recent years, advances in technology and in the area of computer architecture have resulted in increasingly more complex designs. As the complexity of the designs increases, simulation becomes the only viable method for gaining insight into the operation of new as well as existing computer systems. One way to meet the excessive processing requirements of detailed computer systems simulations is to execute them on a multiprocessor machine. Computer systems simulations are inherently synchronous and contain significant amounts of inherent parallelism [8]. Hence, the main problem in such simulations is to exploit the available parelelism with the least possible overhead. Unfortunately, both conservative and optimistic asynchronous methods are not appropriate for such simulations because they introduce significant overheads in their attempt to find parallelism [8]. Therefore, we focus our attention on synchronous parallel simulation methods. In this paper we present a synchronous, parallel, event-driven approach (SPSDES). It differs from previous approaches in many ways: (1) it contains a single, global synchronization operation per simulation phase; (2) it introduces a minimum number of kernel operations into the simulation; (3) it allows for efficient processor self-scheduling; and (4) it aggressively exposes parallelism only when a simulation phase does not contain enough parallelism for the processors to exploit. We study the performance of SPaDES by simulating a symmetric multiprocessor (tat-get machine) on a NUMA multiprocessor (hosl machine). The NUMA characteristics of the host machine enable us to study the performance of the method under demanding run-time conditions and to assess the impact of partitioning and scheduling on the efficiency of the parallel simulator. The few kernel operations introduced by SPaDES, the use of a single barrier during each phase, and the exploitation of coarse-grain parallelism are the main reasons SPaDES achieves high performance. Our main concern in this paper is the performance of the proposed method in the simulation of synchronous architectural designs. In Section 2 we present the SPaDES simulation method, and in Section 3 we study its performance, Section 4 contains our conclusions and future research directions.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信