Demodulating binary phase shift keyed signals using programmable logic devices

This paper describes the realisation of a differential BPSK demodulator using a high speed ADC, an EPLD and an EPROM. By incorporating both I and Q data in the demodulation process, a significant improvement in performance is obtained. Computer simulation shows the bit error rate (BER) performance versus received carrier to noise ratio (CNR) is virtually identical to the theoretical performance of a differential phase shift keyed (DPSK) detector. The realisation of the special PLL required, to recover the data clock using an EPLD, a DAC, a conventional loop filter and VCO is described.