Hierarchical test generation for ASIC circuits using macro specification

Increasingly, VLSI or ULSI designs involve the interconnection of complex macros to produce large-scale systems on a chip. The complexity of the macros and the lack of accessibility to the macros in a chip make efficient test methods essential. Existing ATPG programs flatten designs; this discards the testability information at the macro level. The extent to which macro specification can include testability information which will allow efficient generation of test patterns for assemblages of these macros is discussed. A method of constructing a graph model for a gate-level circuit is illustrated. The graph model can be used for test pattern generation. Experimental results on a set of benchmark circuits are presented. They demonstrate that an improvement in ATPG performance is achieved when the graph model is used instead of the flattened gate-level circuit.<>