1.1 v 12位20 ms /s流水线ADC, 1.8 vpp全摆幅，采用0.13 μm CMOS

2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) Pub Date : 2012-11-01 DOI:10.1109/RFIT.2012.6401620

Peiyuan Wan, W. Lang, Rui Jin, Chi Zhang, Pingfen Lin

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引用次数: 1

摘要

前端单位增益1位翻转DAC (FADAC)在12位共享运放大器的流水线ADC中被利用，在1.1 v电源下允许1.8 vpp的全摆幅输入。高输入摆幅，加上FADAC的大反馈因子(≈1)，实现了高分辨率流水线ADC的低电压低功耗设计。原型12位ADC工作在20 ms /s和1.1 v电源下，在3mhz输入下实现了66.4 dB的SNDR和76.7 dB的SFDR。在0.13-μm CMOS中，ADC功耗为5.2 mW，有效面积为0.44 mm2。

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A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-Vpp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm2 in 0.13-μm CMOS.

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2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

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