{"title":"用于DoD/NASA联合天基雷达任务的数字波束形成处理器","authors":"M. Fischman, C. Le, P. Rosen","doi":"10.1109/NRC.2004.1316387","DOIUrl":null,"url":null,"abstract":"The space based radar (SBR) program includes a joint technology demonstration between NASA and the Air Force to design a low-earth orbiting, 2/spl times/50 m L-band (1.26 GHz) radar system for both Earth science and intelligence-related observations. A key subsystem aboard SBR is the electronically-steerable digital beamformer (DBF) network that interfaces between 32 smaller sub-antenna panels in the array and the on-board processing electronics for synthetic aperture radar (SAR) and moving target indication (MTI). In this paper, we describe the development of a field-programmable gate array (FPGA) based DBF processor for handling the algorithmically simple yet computationally intensive inner-product operations for wideband, coherent beamforming across the 50 m length of the array. Tests with an antenna array simulator demonstrate that the beamformer performance metrics (0.07/spl deg/ rms phase precision per channel, -39.0 dB peak sidelobe level) will meet the system-level requirements for SAR and MTI operating modes.","PeriodicalId":268965,"journal":{"name":"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"A digital beamforming processor for the joint DoD/NASA space based radar mission\",\"authors\":\"M. Fischman, C. Le, P. Rosen\",\"doi\":\"10.1109/NRC.2004.1316387\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The space based radar (SBR) program includes a joint technology demonstration between NASA and the Air Force to design a low-earth orbiting, 2/spl times/50 m L-band (1.26 GHz) radar system for both Earth science and intelligence-related observations. A key subsystem aboard SBR is the electronically-steerable digital beamformer (DBF) network that interfaces between 32 smaller sub-antenna panels in the array and the on-board processing electronics for synthetic aperture radar (SAR) and moving target indication (MTI). In this paper, we describe the development of a field-programmable gate array (FPGA) based DBF processor for handling the algorithmically simple yet computationally intensive inner-product operations for wideband, coherent beamforming across the 50 m length of the array. Tests with an antenna array simulator demonstrate that the beamformer performance metrics (0.07/spl deg/ rms phase precision per channel, -39.0 dB peak sidelobe level) will meet the system-level requirements for SAR and MTI operating modes.\",\"PeriodicalId\":268965,\"journal\":{\"name\":\"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NRC.2004.1316387\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2004 IEEE Radar Conference (IEEE Cat. No.04CH37509)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NRC.2004.1316387","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A digital beamforming processor for the joint DoD/NASA space based radar mission
The space based radar (SBR) program includes a joint technology demonstration between NASA and the Air Force to design a low-earth orbiting, 2/spl times/50 m L-band (1.26 GHz) radar system for both Earth science and intelligence-related observations. A key subsystem aboard SBR is the electronically-steerable digital beamformer (DBF) network that interfaces between 32 smaller sub-antenna panels in the array and the on-board processing electronics for synthetic aperture radar (SAR) and moving target indication (MTI). In this paper, we describe the development of a field-programmable gate array (FPGA) based DBF processor for handling the algorithmically simple yet computationally intensive inner-product operations for wideband, coherent beamforming across the 50 m length of the array. Tests with an antenna array simulator demonstrate that the beamformer performance metrics (0.07/spl deg/ rms phase precision per channel, -39.0 dB peak sidelobe level) will meet the system-level requirements for SAR and MTI operating modes.
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