{"title":"高频快速稳定时间比例-积分-导数控制锁相环的建模与仿真","authors":"G. Konwar, T. Bezboruah","doi":"10.1109/EPETSG.2018.8658754","DOIUrl":null,"url":null,"abstract":"In this work, modelling and behavioural simulation of a new high frequency and fast settling time 3rd order proportional-integral-derivative controlled phase-locked loop model is proposed. It is achieved by inserting in parallel a combination of 2nd order passive low pass filter with the proportional-integral-derivative controller. The addition of the proportional-integral-derivative controller changes the characteristics of the conventional phase-locked loop and consequently reduces the settling time of the system. The mathematical model of the proposed phase-locked loop is derived in s-domain to study various aspects such as stability, settling time, phase margin, bandwidth, damping factor and overshoot. The simulation of the proposed model is performed on MATLAB platform. The simulation result shows that settling time of the proposed model is in the range of 0.0194 ns to 0.133 ns and the phase margin is in the range of 37.7 degree to 76.7 degree with damping factor as 0.704. Simulation results also show that the proposed model is highly stable.","PeriodicalId":385912,"journal":{"name":"2018 2nd International Conference on Power, Energy and Environment: Towards Smart Technology (ICEPE)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Some Aspects of Modelling and Simulation of a High Frequency and Fast Settling Time Proportional-Integral-Derivative Controlled Phase-locked Loop\",\"authors\":\"G. Konwar, T. Bezboruah\",\"doi\":\"10.1109/EPETSG.2018.8658754\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, modelling and behavioural simulation of a new high frequency and fast settling time 3rd order proportional-integral-derivative controlled phase-locked loop model is proposed. It is achieved by inserting in parallel a combination of 2nd order passive low pass filter with the proportional-integral-derivative controller. The addition of the proportional-integral-derivative controller changes the characteristics of the conventional phase-locked loop and consequently reduces the settling time of the system. The mathematical model of the proposed phase-locked loop is derived in s-domain to study various aspects such as stability, settling time, phase margin, bandwidth, damping factor and overshoot. The simulation of the proposed model is performed on MATLAB platform. The simulation result shows that settling time of the proposed model is in the range of 0.0194 ns to 0.133 ns and the phase margin is in the range of 37.7 degree to 76.7 degree with damping factor as 0.704. Simulation results also show that the proposed model is highly stable.\",\"PeriodicalId\":385912,\"journal\":{\"name\":\"2018 2nd International Conference on Power, Energy and Environment: Towards Smart Technology (ICEPE)\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 2nd International Conference on Power, Energy and Environment: Towards Smart Technology (ICEPE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPETSG.2018.8658754\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 2nd International Conference on Power, Energy and Environment: Towards Smart Technology (ICEPE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPETSG.2018.8658754","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Some Aspects of Modelling and Simulation of a High Frequency and Fast Settling Time Proportional-Integral-Derivative Controlled Phase-locked Loop
In this work, modelling and behavioural simulation of a new high frequency and fast settling time 3rd order proportional-integral-derivative controlled phase-locked loop model is proposed. It is achieved by inserting in parallel a combination of 2nd order passive low pass filter with the proportional-integral-derivative controller. The addition of the proportional-integral-derivative controller changes the characteristics of the conventional phase-locked loop and consequently reduces the settling time of the system. The mathematical model of the proposed phase-locked loop is derived in s-domain to study various aspects such as stability, settling time, phase margin, bandwidth, damping factor and overshoot. The simulation of the proposed model is performed on MATLAB platform. The simulation result shows that settling time of the proposed model is in the range of 0.0194 ns to 0.133 ns and the phase margin is in the range of 37.7 degree to 76.7 degree with damping factor as 0.704. Simulation results also show that the proposed model is highly stable.