高频快速稳定时间比例-积分-导数控制锁相环的建模与仿真

G. Konwar, T. Bezboruah
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引用次数: 3

摘要

本文提出了一种新的高频、快速稳定时间的三阶比例-积分-导数控制锁相环模型的建模和行为仿真。它是通过并联插入二阶无源低通滤波器和比例积分导数控制器的组合来实现的。比例-积分-导数控制器的加入改变了传统锁相环的特性,从而缩短了系统的稳定时间。在s域建立了锁相环的数学模型,研究了锁相环的稳定性、稳定时间、相位裕度、带宽、阻尼系数和超调量等方面的特性。在MATLAB平台上对该模型进行了仿真。仿真结果表明,该模型的沉降时间范围为0.0194 ~ 0.133 ns,相位裕度范围为37.7 ~ 76.7°,阻尼系数为0.704。仿真结果表明,该模型具有较高的稳定性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Some Aspects of Modelling and Simulation of a High Frequency and Fast Settling Time Proportional-Integral-Derivative Controlled Phase-locked Loop
In this work, modelling and behavioural simulation of a new high frequency and fast settling time 3rd order proportional-integral-derivative controlled phase-locked loop model is proposed. It is achieved by inserting in parallel a combination of 2nd order passive low pass filter with the proportional-integral-derivative controller. The addition of the proportional-integral-derivative controller changes the characteristics of the conventional phase-locked loop and consequently reduces the settling time of the system. The mathematical model of the proposed phase-locked loop is derived in s-domain to study various aspects such as stability, settling time, phase margin, bandwidth, damping factor and overshoot. The simulation of the proposed model is performed on MATLAB platform. The simulation result shows that settling time of the proposed model is in the range of 0.0194 ns to 0.133 ns and the phase margin is in the range of 37.7 degree to 76.7 degree with damping factor as 0.704. Simulation results also show that the proposed model is highly stable.
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