高k栅极电介质的可靠性问题

A. Oates
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引用次数: 43

摘要

在不久的将来,高k栅极介电材料有可能在硅CMOS工艺中实现。接近或超过SiO/ sub2 /的可靠性特性将是未来开发工作的主要目标之一。本文综述了高钾栅极电介质可靠性的研究现状。高k材料表现出与不对称栅带结构和固定电荷的存在有关的新的可靠性现象。高k结构的可靠性受界面层和高k层的双重影响。实现可靠性目标需要消除充电效应,这是晶体管退化的主要原因。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reliability issues for high-k gate dielectrics
High-k gate dielectric materials are likely to be implemented in Si CMOS processes in the near future. Reliability characteristics that closely match, or exceed, those of SiO/sub 2/ will be one of the primary goals of future development work. In this paper we review the status of reliability studies of high-k gate dielectrics. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fixed charge. The reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. Attainment of reliability goals will require elimination of charging effects, which dominate transistor degradation.
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