{"title":"具有数字背景校准的延迟锁定环","authors":"Wei-Ming Lin, K. Teng, Shen-Iuan Liu","doi":"10.1109/ASSCC.2009.5357157","DOIUrl":null,"url":null,"abstract":"A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18μm technology. The measured input frequency range of this DLL is from 400MHz to 525MHz. The measured static phase error without and with calibration is 113.8ps and 27.8ps, respectively, at 525MHz. The measured peak-to-peak jitter without and with calibration is 15.56ps and 15.11ps, respectively. The power consumption is 25.2mW at 500MHz and the area is 0.85mm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A delay-locked loop with digital background calibration\",\"authors\":\"Wei-Ming Lin, K. Teng, Shen-Iuan Liu\",\"doi\":\"10.1109/ASSCC.2009.5357157\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18μm technology. The measured input frequency range of this DLL is from 400MHz to 525MHz. The measured static phase error without and with calibration is 113.8ps and 27.8ps, respectively, at 525MHz. The measured peak-to-peak jitter without and with calibration is 15.56ps and 15.11ps, respectively. The power consumption is 25.2mW at 500MHz and the area is 0.85mm2.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357157\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A delay-locked loop with digital background calibration
A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18μm technology. The measured input frequency range of this DLL is from 400MHz to 525MHz. The measured static phase error without and with calibration is 113.8ps and 27.8ps, respectively, at 525MHz. The measured peak-to-peak jitter without and with calibration is 15.56ps and 15.11ps, respectively. The power consumption is 25.2mW at 500MHz and the area is 0.85mm2.
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