A FPGA-Pipelined, High-Throughput Approach to Coarse-Grained Simulation of HPC Systems

Although previous studies have accelerated discreteevent simulation with various parallelization strategies, total simulation time remains prohibitive for certain use cases that require many independent simulations (e.g., design-space exploration, Monte Carlo simulation). In this paper, rather than focus solely on improved execution time for an individual simulation, we introduce an FPGA-accelerated approach that potentially sacrifices simulation latency to greatly increase throughput by many orders of magnitude. In this approach, the simulation design space is converted to an intermediate dataflow graph representation and ultimately mapped to a simulation pipeline by a custom-built compiler. We describe the design and implementation of our approach. Additionally, we present a resourcesharing strategy that greatly increases design scalability at the cost of slightly reduced simulation throughput. Although not applicable in all scenarios, we demonstrate that this approach can accelerate total simulation time for design-space exploration of HPC algorithmic/architectural co-design by up to 6 orders of magnitude when compared to the same exploration performed with a parallel software simulator.