{"title":"电阻网络快速分段线检测器的FPGA实现","authors":"A. Abdallah, D. Felici, G. Aielli, R. Cardarelli","doi":"10.1109/ICM.2017.8268837","DOIUrl":null,"url":null,"abstract":"In this article we present a Field Programmable Gate Arrays (FPGA) implementation inspired by a weighting resistor matrix (WRM) for fast discrete segment line detection in digital images. The implementation proposed here achieves both real time processing and very good performance, taking advantage of the flexibility and the fast deployment of the FPGA for real time segment detection applications.","PeriodicalId":115975,"journal":{"name":"2017 29th International Conference on Microelectronics (ICM)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"FPGA implementation of resistor network for fast segment line detector\",\"authors\":\"A. Abdallah, D. Felici, G. Aielli, R. Cardarelli\",\"doi\":\"10.1109/ICM.2017.8268837\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this article we present a Field Programmable Gate Arrays (FPGA) implementation inspired by a weighting resistor matrix (WRM) for fast discrete segment line detection in digital images. The implementation proposed here achieves both real time processing and very good performance, taking advantage of the flexibility and the fast deployment of the FPGA for real time segment detection applications.\",\"PeriodicalId\":115975,\"journal\":{\"name\":\"2017 29th International Conference on Microelectronics (ICM)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 29th International Conference on Microelectronics (ICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2017.8268837\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 29th International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2017.8268837","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA implementation of resistor network for fast segment line detector
In this article we present a Field Programmable Gate Arrays (FPGA) implementation inspired by a weighting resistor matrix (WRM) for fast discrete segment line detection in digital images. The implementation proposed here achieves both real time processing and very good performance, taking advantage of the flexibility and the fast deployment of the FPGA for real time segment detection applications.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
