{"title":"数字DS-CDMA接收机工作在芯片速率以下","authors":"I. Maravic, M. Vetterli","doi":"10.1109/ACSSC.2002.1197022","DOIUrl":null,"url":null,"abstract":"We consider the problem of designing low-complexity digital receivers for CDMA systems operating over channels with single or multiple propagation paths. We extend some of our recent sampling results for certain classes of non-bandlimited signals and develop a method that takes advantage of transform techniques to perform channel estimation and signal detection from a low-dimensional subspace of a received signal, that is, by sampling below the traditional Nyquist rate. By lowering the sampling rate we can reduce computational requirements compared to existing solutions, allow for slower A/D converters and significantly reduce the power consumption of digital receivers. In effect, we use an algorithmic solution to improve hardware specifications in terms of complexity and power.","PeriodicalId":284950,"journal":{"name":"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Digital DS-CDMA receivers working below the chip rate\",\"authors\":\"I. Maravic, M. Vetterli\",\"doi\":\"10.1109/ACSSC.2002.1197022\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We consider the problem of designing low-complexity digital receivers for CDMA systems operating over channels with single or multiple propagation paths. We extend some of our recent sampling results for certain classes of non-bandlimited signals and develop a method that takes advantage of transform techniques to perform channel estimation and signal detection from a low-dimensional subspace of a received signal, that is, by sampling below the traditional Nyquist rate. By lowering the sampling rate we can reduce computational requirements compared to existing solutions, allow for slower A/D converters and significantly reduce the power consumption of digital receivers. In effect, we use an algorithmic solution to improve hardware specifications in terms of complexity and power.\",\"PeriodicalId\":284950,\"journal\":{\"name\":\"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.2002.1197022\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.2002.1197022","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Digital DS-CDMA receivers working below the chip rate
We consider the problem of designing low-complexity digital receivers for CDMA systems operating over channels with single or multiple propagation paths. We extend some of our recent sampling results for certain classes of non-bandlimited signals and develop a method that takes advantage of transform techniques to perform channel estimation and signal detection from a low-dimensional subspace of a received signal, that is, by sampling below the traditional Nyquist rate. By lowering the sampling rate we can reduce computational requirements compared to existing solutions, allow for slower A/D converters and significantly reduce the power consumption of digital receivers. In effect, we use an algorithmic solution to improve hardware specifications in terms of complexity and power.