基于CMOS 130nm技术的低功耗4T SRAM单元

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN) Pub Date : 2016-12-01 DOI:10.1109/CICN.2016.121

Anshul Goyal, V. Agarwal

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引用次数: 1

摘要

近年来，SRAM由于存储容量大、存取时间短而成为许多VLSI芯片的主要组成部分。功耗是SRAMCMOS片上系统设计的主要问题。功耗也影响芯片设计和SRAM的速度。在本文中，我们提出了4TSRAM电池，能够降低功耗和面积。从结果会话中我们可以看到，与6T SRAM Cell相比，4T SRAM Cell的功耗降低了36%。

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Low Power Consumption Based 4T SRAM Cell for CMOS 130nm Technology

In the Recent time, SRAM became a major componentfor many VLSI Chips due to big storage memory and low accesstime. Power Consumption is the major issue for design the SRAMCMOS design System on Chip. Power consumption also effects thechip design and Speed of the SRAM. In this paper, we propose 4TSRAM Cell which is able to reduce the power consumption andArea also. As we can see from the results session, powerconsumption of the 4T SRAM Cell get reduce up to 36% ascompare to 6T SRAM Cell.

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2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)

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