Design and Analysis of Approximate Multipliers for Error-Tolerant Applications

In applications such as image and video processing, the final output is interpreted by human eyes, which are insensible to small errors in the output. In these cases, approximate circuits play a vital role in achieving low power and high speed designs with small errors in the output. In this paper, three approximate full-adder designs are proposed and they are reused to design approximate Dadda multipliers. For generating partial products in the multiplier, a newly designed AND gate approach is proposed. All the proposed designs are simulated using 90nm UMC technology. The Simulation results indicate that the number of transistors and power consumption of approximate multipliers are reduced by 28% and 32% respectively as compared to conventional Dadda multiplier. This paper also analyses the errors at the multiplier output using different error metrics.