{"title":"基于门控d型锁锁的银行储物柜集成安全系统","authors":"Silpakesav Velagaleti","doi":"10.1109/INOCON57975.2023.10101343","DOIUrl":null,"url":null,"abstract":"This paper discusses the design of a Bank locker system. Three different versions of a Bank Locker Security (BLS) System is designed and observed the power consumption at different process corners and different supply voltages. The simulations are measured at 27o C temperature. The power consumption is observed at the supply voltage from 600mV to 1. 2V. The power consumption is less with slow-slow (SS) process corner at 66 MHZ and 200 MHz respectively. This BLS is designed using 45nm CMOS technology.","PeriodicalId":113637,"journal":{"name":"2023 2nd International Conference for Innovation in Technology (INOCON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Integrated Security System for Bank Lockers Using Gated D-Latch\",\"authors\":\"Silpakesav Velagaleti\",\"doi\":\"10.1109/INOCON57975.2023.10101343\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper discusses the design of a Bank locker system. Three different versions of a Bank Locker Security (BLS) System is designed and observed the power consumption at different process corners and different supply voltages. The simulations are measured at 27o C temperature. The power consumption is observed at the supply voltage from 600mV to 1. 2V. The power consumption is less with slow-slow (SS) process corner at 66 MHZ and 200 MHz respectively. This BLS is designed using 45nm CMOS technology.\",\"PeriodicalId\":113637,\"journal\":{\"name\":\"2023 2nd International Conference for Innovation in Technology (INOCON)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 2nd International Conference for Innovation in Technology (INOCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INOCON57975.2023.10101343\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 2nd International Conference for Innovation in Technology (INOCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INOCON57975.2023.10101343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Integrated Security System for Bank Lockers Using Gated D-Latch
This paper discusses the design of a Bank locker system. Three different versions of a Bank Locker Security (BLS) System is designed and observed the power consumption at different process corners and different supply voltages. The simulations are measured at 27o C temperature. The power consumption is observed at the supply voltage from 600mV to 1. 2V. The power consumption is less with slow-slow (SS) process corner at 66 MHZ and 200 MHz respectively. This BLS is designed using 45nm CMOS technology.
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