通过分段替换减少延迟

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC Pub Date : 1994-02-28 DOI:10.1109/EDTC.1994.326894

Hitesh Ajuha, P. R. Menon

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引用次数: 1

摘要

本文提出了一种通过结构修改来降低组合电路延迟的新算法。通过将电路中最长路径的延迟低效段替换为执行相同功能的更快段，可以获得延迟减少。在ISCAS85基准电路上的实验结果表明，该电路仅增加了适度的面积，就能很好地降低延迟。将这种方法推广到技术映射电路的延迟降低上是可行的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Delay reduction by segment substitution

This paper presents a new algorithm for reducing the delay of combinational circuits by structural modifications. Delay reduction is obtained by substituting delay-inefficient segments of the longest path in the circuit, by faster segments which perform the same function. Experimental results with the ISCAS85 benchmark circuits showed good delay reduction with only moderate area increase. Extension of this method for delay reduction of technology-mapped circuits appears to be feasible.<>

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来源期刊

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

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