用Verilog实现双精度浮点数加减模块的FPGA实现

Sonali M. Rane, T. Wagh, P. Malathi
{"title":"用Verilog实现双精度浮点数加减模块的FPGA实现","authors":"Sonali M. Rane, T. Wagh, P. Malathi","doi":"10.1109/ICAETR.2014.7012850","DOIUrl":null,"url":null,"abstract":"The floating point operations are critical to implement on FPGAs due to their complexity of their algorithms. Thus, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, in this paper the proposed work is explored FPGA implementation of Addition/Subtraction for IEEE double precision floating point numbers. This kind of unit can be extremely useful in the FPGA implementation of complex systems that benefits from the parallelism of the FPGA device. The design is in Verilog Hardware description language (HDL) and implemented on FPGA. The verilog code first simulated with isim and synthesized on Xilinx ISE14.1i.","PeriodicalId":196504,"journal":{"name":"2014 International Conference on Advances in Engineering & Technology Research (ICAETR - 2014)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"FPGA implementation of Addition/Subtraction module for double precision floating point numbers using Verilog\",\"authors\":\"Sonali M. Rane, T. Wagh, P. Malathi\",\"doi\":\"10.1109/ICAETR.2014.7012850\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The floating point operations are critical to implement on FPGAs due to their complexity of their algorithms. Thus, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, in this paper the proposed work is explored FPGA implementation of Addition/Subtraction for IEEE double precision floating point numbers. This kind of unit can be extremely useful in the FPGA implementation of complex systems that benefits from the parallelism of the FPGA device. The design is in Verilog Hardware description language (HDL) and implemented on FPGA. The verilog code first simulated with isim and synthesized on Xilinx ISE14.1i.\",\"PeriodicalId\":196504,\"journal\":{\"name\":\"2014 International Conference on Advances in Engineering & Technology Research (ICAETR - 2014)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Advances in Engineering & Technology Research (ICAETR - 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAETR.2014.7012850\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Advances in Engineering & Technology Research (ICAETR - 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAETR.2014.7012850","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

由于其算法的复杂性,浮点运算在fpga上的实现至关重要。因此,许多科学问题的计算都需要高精度的浮点运算。因此,本文提出的工作是探索FPGA实现IEEE双精度浮点数的加减运算。这种单元在复杂系统的FPGA实现中非常有用,这得益于FPGA器件的并行性。该设计采用Verilog硬件描述语言(HDL),在FPGA上实现。verilog代码首先用isim进行仿真,然后在Xilinx is14.1 i上进行合成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
FPGA implementation of Addition/Subtraction module for double precision floating point numbers using Verilog
The floating point operations are critical to implement on FPGAs due to their complexity of their algorithms. Thus, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, in this paper the proposed work is explored FPGA implementation of Addition/Subtraction for IEEE double precision floating point numbers. This kind of unit can be extremely useful in the FPGA implementation of complex systems that benefits from the parallelism of the FPGA device. The design is in Verilog Hardware description language (HDL) and implemented on FPGA. The verilog code first simulated with isim and synthesized on Xilinx ISE14.1i.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信