记忆电容神经形态回路多域尖峰编码的初步评价

Reon Oshio, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Y. Nakashima
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引用次数: 1

摘要

神经形态计算采用比人工神经网络(ANN)更具生物学合理性的峰值神经网络(SNN)硬件架构,旨在加速机器学习计算并降低其功耗。速率编码snn根据尖峰的频率表示信号,它与人工神经网络具有很高的兼容性,并且可以利用近年来积累的技术。然而,使用大量尖峰的速率编码snn存在延迟长和功耗增加的问题,因此寻找更有效的编码方法已经成为一种活跃的研究方向。在这项研究中,我们提出了一种新的编码方案,不仅使用尖峰的频率,还使用尖峰的电压幅度和时间宽度,这些都是传统snn中未使用的域。与普通速率编码相比,所提出的多域神经编码可以增加每尖峰可以传输的信息量。此外,基于电导的突触器件/电路(如忆阻器)已被广泛研究,但基于电流的突触操作消耗大量功率。在这项工作中,我们采用了memcapacitor和基于电荷泵的突触电路,这是一种电压域突触操作,理想情况下仅在开关过程中消耗功率。我们通过在HSPICE上模拟操作,对采用ROHM 180nm CMOS工艺设计的突触/神经元电路的编码方案进行了初步评估。此外,所提出的电路可以成功地执行突触操作,以允许新的编码方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Preliminary Evaluation for Multi-domain Spike Coding on Memcapacitive Neuromorphic Circuit
Neuromorphic computing aims at both accelerating machine learning computation and reducing its power consumption by adopting the hardware architecture of Spiking Neural Network (SNN), which is more biologically plausible than Artificial Neural Network (ANN). Rate coded SNNs, which represent signals according to the frequency of spikes, are highly compatible with ANNs and can utilize the technology accumulated in recent years. However, rate coded SNNs using a large number of spikes suffer from long latency and increased power consumption, and the search for a more efficient coding method has become active. In this study, we propose a novel coding scheme that uses not only the frequency of spikes but also the voltage amplitude and time width of spikes, which are domains that have not been used in conventional SNNs. The proposed multi-domain neural coding can be expected to increase the amount of information that can be transmitted per spike compared to ordinary rate coding. In addition, conductance-based synaptic devices/circuits like memristor have been widely studied, but current-based synaptic operations consume a lot of power. In this work, we employed memcapacitor and charge-pump based synapse circuit, which is a voltage-domain synaptic operation that ideally consumes power only during switching. We have performed a preliminary evaluation for the proposed coding scheme on a synaptic/neuron circuit designed in a ROHM 180nm CMOS process by simulating the operation on HSPICE. Moreover it was demonstrated that the proposed circuit can successfully perform synaptic operations to allow the new coding scheme.
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