使用JACK对UML状态图进行模型检查

Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering Pub Date : 1999-11-17 DOI:10.1109/HASE.1999.809474

S. Gnesi, D. Latella, M. Massink

{"title":"使用JACK对UML状态图进行模型检查","authors":"S. Gnesi, D. Latella, M. Massink","doi":"10.1109/HASE.1999.809474","DOIUrl":null,"url":null,"abstract":"Statechart diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modelling Language (UML). In this paper, we present a branching-time model-checking approach to the automatic verification of the formal correctness of UML Statechart diagram specifications. We use a formal operational semantics for building a labelled transition system (automaton) which is then used as a model to be checked against correctness requirements expressed in Action-Based Temporal Logic (ACTL). Our reference verification environment is JACK, where automata are represented in a standard format, which facilitates the use of different tools for automatic verification.","PeriodicalId":369187,"journal":{"name":"Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"95","resultStr":"{\"title\":\"Model checking UML Statechart diagrams using JACK\",\"authors\":\"S. Gnesi, D. Latella, M. Massink\",\"doi\":\"10.1109/HASE.1999.809474\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Statechart diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modelling Language (UML). In this paper, we present a branching-time model-checking approach to the automatic verification of the formal correctness of UML Statechart diagram specifications. We use a formal operational semantics for building a labelled transition system (automaton) which is then used as a model to be checked against correctness requirements expressed in Action-Based Temporal Logic (ACTL). Our reference verification environment is JACK, where automata are represented in a standard format, which facilitates the use of different tools for automatic verification.\",\"PeriodicalId\":369187,\"journal\":{\"name\":\"Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"95\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HASE.1999.809474\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HASE.1999.809474","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 95

摘要

状态图为在统一建模语言(UML)中描述系统行为的动态方面提供了一种图形化的符号。在本文中，我们提出了一种分支时间模型检查方法来自动验证UML状态图规范的形式正确性。我们使用形式化的操作语义来构建标记转换系统(自动机)，然后将其用作模型，根据基于动作的时间逻辑(ACTL)中表达的正确性要求进行检查。我们的参考验证环境是JACK，其中自动机以标准格式表示，这有助于使用不同的工具进行自动验证。

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Model checking UML Statechart diagrams using JACK

Statechart diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modelling Language (UML). In this paper, we present a branching-time model-checking approach to the automatic verification of the formal correctness of UML Statechart diagram specifications. We use a formal operational semantics for building a labelled transition system (automaton) which is then used as a model to be checked against correctness requirements expressed in Action-Based Temporal Logic (ACTL). Our reference verification environment is JACK, where automata are represented in a standard format, which facilitates the use of different tools for automatic verification.

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Proceedings 4th IEEE International Symposium on High-Assurance Systems Engineering

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