An efficient on-chip network with packet compression capability

In order to reduce inter-core data communication load, increase effective bandwidth, reduce storage space and power consumption, various solutions have been suggested for on-chip networks. The aim of this study is to employ data compression for the packets delivered between cores over the inter-core on-chip network. The packets transferring the cache lines between cores are compressed before transmission. We use a full-system simulator to evaluate and compare different systems that employ different compression methods.